In recent years, in the fields of consumer electronics, advanced communication devices, and the like, the interface of semiconductor memory has been changing from a single data rate (SDR) that enables operation at the same speed as clock signals to a double data rate (DDR) that enables operation at a speed twice as fast as clock signals. In the DDR memory interface, read data is taken in using both rising and falling edges of a clock signal. Accordingly, a precise delay circuit to match a rising edge or a falling edge of a clock signal with a defined part of the data is required. Among such precise delay circuits is a digital DLL circuit.
FIG. 23 is a schematic depicting a configuration of a conventional digital DLL circuit. As depicted in FIG. 23, the conventional digital DLL circuit includes a reference-delay determining circuit 1 and a delay output circuit 2, separately. The reference-delay determining circuit 1, using a phase-comparing/reference-delay-determining circuit 4 and while changing the number of delay lines in the delay line unit 3, compares the phases of a clock signal subject to delay measurement (hereinafter, “delay-measurement clock signal”) before and after the clock signal passes through a delay line unit 3, to determine a reference delay value. The reference delay value is given to multiple delay output circuits 2 as a digitalized value expressed by a predetermined number of bits.
The delay output circuit 2 determines a final delay value by a final-delay-value determining circuit 5, based on the reference delay value given by the reference-delay determining circuit 1 and a delay angle set externally. The delay output circuit 2 sets the final delay value in a delay line unit 6 that is in the delay output circuit 2. Thus, a delay of, for example, 90 degrees is induced on a data strobe (DQS) signal that has passed the delay line unit 6 of the delay output unit 2 at the time of data read, as described later.
FIG. 24 is a schematic for explaining a principle of a delay measuring method by conventional phase comparison, and FIG. 25 is a view of waveforms at the time of delay measurement. As depicted in FIG. 24, in the phase comparison, while changing the number of delay lines 8 of a delay line unit 7 through which a delay measurement clock signal passes, a phase comparing circuit 9 compares a phase of a delay measurement clock signal that has not passed the delay line unit 7 and a phase of a delay measurement clock signal (hereinafter, “delay clock signal”) that has passed the delay line unit 7.
As depicted in FIG. 25, when the result of the phase comparison indicates that the value of a delay clock signal 12 is at a high (H) level at a rising edge in the subsequent cycle of a delay measurement clock signal 11, delay is regarded to be insufficient, and when the result indicates that the value of a delay clock signal 14 is at a low (L) level, delay is regarded to be excessive. When optimal delay is induced, the rising edge of the delay measurement clock signal 11 corresponds with a changing portion of a delay clock signal 13.
A phase comparing circuit latches a state of a delay clock signal in synchronization with the rising edge of the delay measurement clock signal by a flip-flop. When configuration of the circuit is such to confirm the value of the delay clock signal at this time, the value latched by the flip-flop becomes unstable (H level or L level) when the optimal delay is induced. Therefore, typically, the phase comparison of the delay measurement clock signal and a delay clock signal is performed for three cases in which the number of the delay lines is [m−1], m, and [m+1], and based on three values acquired from the comparison, the number of the delay lines that is required to optimize the delay is acquired.
FIG. 26 is a time chart at the time of memory read in a typical DDR memory interface. A digital DLL circuit is used to induce delay on a data strobe signal in order to ensure acquisition of read data at the time of read data based on the data strobe signal that is a memory access signal output from a memory. Ideally, timing in which a 90-degree delay is induced on the data strobe signal is desirable as depicted in FIG. 26 by “data output” and “DQS after a phase shift of 90 degrees” because such timing is a central point of a data determination area.
The number of delay lines required to induce a delay of 360 degrees, that is, one cycle of the delay measurement clock signal, is calculated by measurement, such as the phase comparison described above, and the like. Because the cycle of a data strobe signal is the same as the cycle of the delay measurement clock signal, the value to induce a delay of 90 degrees to the data strobe signal is ¼ of the value to induce a delay of 360 degrees to the delay measurement clock signal. Specifically, when 256 delay lines are required to generate delay of 360 degrees, for example, 64 delay lines, which is ¼ of 256, are required to generate a delay of 90 degrees.
Moreover, in the DDR memory interface, if the phase of the data strobe signal shifts 180 degrees or more, a data area that is captured at the subsequent edge of the data strobe signal is entered, and therefore, a delay of 180 degrees or more is not to be induced on the data strobe signal. Accordingly, as depicted in FIG. 23, half of the number of the delay lines (for 360 degrees) in the delay line unit 3 of the reference-delay determining circuit 1 is enough for the number of delay lines in the delay line unit 6 of the delay output circuit 2.
A clock generating circuit is conventionally known that generates multiple delay clocks having a cycle identical to that of a basic clock signal (for example, Japanese Laid-Open Patent Publication No. H8-321753). The delay-clock generating circuit includes cascade-connected n stages of delay circuits that sequentially delay the basic clock (n is an integer equal to or larger than 2), a phase comparing circuit that compares phases between a delay clock obtained through the n-th delay circuit and the basic clock, and a delay control circuit that generates a delay value to synchronize phases of the delay clock from the n-th delay circuit and the basic clock, and that controls an amount of delay of each of the n stages of the delay circuits by the delay value.
However, in the conventional digital DLL circuit, because the reference delay determining circuit and the delay output circuit are provided separately, various problems arise. A process condition at manufacturing, or a temperature or voltage condition at actual utilization can vary in the both circuits, and the delay output circuit cannot accurately generate the delay determined by delay measurement performed by the reference-delay determining circuit. Furthermore, because the reference delay determining circuit and the delay output circuit have delay lines separately, the scale of the circuit is large. In addition, if the scale of the DLL circuit is large, power consumption increases. Moreover, update of the delay value when delay is induced on the data strobe signal in the delay output circuit causes malfunction.